This application claims priority to an application entitled xe2x80x9cFrequency Synthesizerxe2x80x9d filed in the Japanese Patent Office on Mar. 2, 2001 and assigned Serial No. 2001-58395, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates generally to a frequency synthesizer for generating a sine wave and a cosine wave by digital signal processing, and a frequency synthesizer capable of reducing spurious signals.
2. Description of the Related Art
When a direct digital synthesizer (DDS) is used in generating a local signal of a receiver, spurious signals generated by operation of the DDS deteriorate an adjacent channel interference characteristic and an outband interference characteristic. Likewise, when the DDS is used to generate a local signal of a transmitter, the spurious signals interfere with adjacent frequencies.
FIG. 6 illustrates how spurious signals are generated in a conventional DDS. The spurious signals caused by insufficient operation accuracy of the DDS are generated because of: (i) a phase requantization error ep due to a difference between an operation word length j of a phase operator comprised of an adder 71 and a phase register 72, and an address length k of a ROM (Read Only Memory) 73 for converting phase data to amplitude data; and (ii) an amplitude quantization error ea of output bits of the ROM 73. As illustrated in FIG. 7, the spurious signals are uniformly distributed around a frequency fc of a desired signal. If the operation word length j is set to be equal to the address length k (j=k) to improve the operation accuracy of the DDS, no spurious signal will be generated. Further, if an output data with a width m of the ROM 73, as illustrates in FIG. 6, is set to a sufficiently large value, the spurious signals caused by the amplitude error will have a negligible level.
However, when the operation word length j of the phase operator is set to be equal to the address length k of the ROM 73, the ROM size is doubled each time the address length k is increased by one bit. Therefore, it is difficult to realize the ROM 73 when the operation word length is relatively long. Accordingly, a method using the addition theorem of a trigonometric function has been proposed as a method for realizing an equivalent large ROM size with an actual small ROM size. For example, if j0-bit frequency setting data is F=A+B, where A represents data of j1 bits on the MSB (Most Significant Bit) side and B represents data of remaining j2 bits on the LSB (Least Significant Bit) side, then cos(F) and sin(F) are defined as
cos(F)=cos(A+B)=cos Axc2x7cos Bxe2x88x92sin Axc2x7sin B
sin(F)=sin(A+B)=sin Axc2x7cos B+cos Axc2x7sin B
That is, the frequency setting data F can be generated by synthesizing the frequency setting data A and the frequency setting data B in accordance with the above formulas. For example, in the case where the frequency setting data F is comprised of 16 bits, even though the output data width m of the ROM 73 is 1 bit (m=1), the ROM 73 requires a capacity of 64 K wordsxc3x972, as shown in the following formulas.
(1) For cos(F), 216 words=65,536 words
(2) For sin(F), 216 words=65,536 words
However, if the 16-bit frequency setting data F is divided into 8-bit frequency setting data A and 8-bit frequency setting data B, the required ROM capacity becomes 256 words, a square root of 65,536 words, as shown in the following formulas.
(2) For cos(A), 256 words
(2) For sin(A), 256 words
(3) For cos(B), 256 words
(4) For sin(B), 256 words
That is, since the required total capacity becomes 256 wordsxc3x974, the required ROM size becomes {fraction (1/128)} times the ROM size of the conventional DDS.
FIG. 8 illustrates a structure of a DDS using the addition theorem of a trigonometric function according to the prior art. As illustrated, when j0-bit frequency setting data F represented by a phase variation width xcex94xcfx86 is received, a phase operator comprised of an adder 51 and a phase register 52 accumulates the frequency setting data F into phase data Ff. The j0-bit phase data Ff is separated into j1-bit phase data Af and j2-bit phase data Bf starting from the MSB side, and k1 bits in the separated j1-bit phase data Af on the MSB side are applied as address signals to a coarse cos(A) ROM-A 53 and a coarse sin(A) ROM-B 54, in each of which a table for converting phase data to amplitude data is stored. The ROM-A 53 and the ROM-B 54 sequentially output m-bit amplitude data, respectively. Here, the ROM-A 53 and the ROM-B 54 register quantized cosine and sine waves of a frequency corresponding to the j1 bits on the MSB side of the phase data Ef, respectively.
Meanwhile, k2 bits in the remaining j2-bit phase data Bf are applied as address signals to a fine cos(B) ROM-C 55 and a fine sin(B) ROM-D 56, in each of which a table for converting phase data to amplitude data is stored. The ROM-C 55 and the ROM-D 56 sequentially output m-bit amplitude data, respectively. Here, the ROM-C 55 and the ROM-D 56 register quantized cosine and sine waves of a frequency corresponding to the remaining j2 bits of the phase data Ef, respectively. A complex mixer 57 synthesizes the m-bit amplitude data outputs from the ROM-A 53, ROM-B 54, ROM-C 55 and ROM-D 56, and generates output signals cos(n) and sin(n) of the frequency synthesizer. In order to calculate a real-part output signal, the complex mixer 57 includes a multiplier 58 for multiplying a real-part input signal T1 by a real-part input signal T3, a multiplier 59 for multiplying an imaginary-part input signal T2 by an imaginary-part input signal T4, and a subtracter 60 for synthesizing an output of the multiplier 58 and an output of the multiplier 59. Further, in order to calculate an imaginary-part output signal, the complex mixer 57 includes a multiplier 61 for multiplying the real-part input signal T1 by the imaginary-part input signal T4, a multiplier 62 for multiplying the real-part input signal T3 by the imaginary-part input signal T2, and an adder 63 for synthesizing an output of the multiplier 61 and an output of the multiplier 62. The output of the ROM-A 53 is connected to a terminal T1 of the complex mixer 57, the output of the ROM-B 54 to a terminal T2 of the complex mixer 57, the output of the ROM-C 55 to a terminal T3 of the complex mixer 57, and the output of the ROM-D 56 to a terminal T4 of the complex mixer 57. As a result, the frequency synthesizer of FIG. 8 outputs carrier signals cos(n) and sin(n) with a frequency corresponding to the frequency setting data F=A+B.
However, when the frequency setting data F needs 32 bits, 232=4,294,967,296 words and a square root of 4,294,967,296 words is 65,536 words. Even though the frequency setting data F is divided into data A and data B, a 64K wordsxc3x974=256K word-ROM is required. Thus, the DDS cannot implement the high-speed operation. When a desired operation word length of the frequency setting data F is increased, it is difficult to set an address length k1 of a ROM for converting frequency setting data A to amplitude data and an address length k2 of a ROM for converting frequency setting data B to amplitude data such that j1=k1 and j2=k2. As a result, j1 greater than k1 and j2 greater than k2. In this case, since the ROM size is smaller than when the frequency is not divided, it is possible to reduce error generated. However, since phase errors are generated in the frequency setting data A and the frequency setting data B, generation of the spurious signals is unavoidable.
In particular, the spurious signals of the DDS are uniformly distributed as illustrated in FIG. 7. Thus, when used as a local signal generator of a radio communication apparatus, the DDS undergoes interference over a wide range in a receiver and causes interference over a wide range in a transmitter. This is symmetrical considering that spurious signals of an analog oscillator generally have a negligibly low level in a point far way from a signal although a carrier-to-noise ratio (C/N) is not high in the vicinity of the signal.
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a frequency synthesizer for improving a unique DDS characteristic, while maintaining a circuit scale (ROM size) of a direct digital synthesizer (DDS).
To achieve the above and other objects, the preset invention provides a frequency synthesizer for a radio communication system comprising a first digital signal generator for generating a quantized frequency signal; a second digital signal generator for generating a frequency signal having a fine frequency resolution and many spurious signals as compared with the first digital signal generator; a filter for performing band rejection on an output of the second digital signal generator; and a mixer for mixing an output of the first digital signal generator with an output of the filter.